This application claims the benefit of Korean Patent Application No. 2001-35701, filed Jun. 22, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
This invention relates to integrated circuit devices and fabrication methods, and more particularly Read Only Memory (ROM) devices and fabrication methods therefor.
Integrated circuit Read Only Memory (ROM) devices are widely used for storing programs and/or data in a nonvolatile manner. Once data is programmed into a ROM device, it remains permanently in the ROM device and can be read but generally cannot be overwritten. As is well known to those having skill in the art, a ROM generally includes a transistor array in a cell region, wherein individual transistors are programmed to store a one or a zero using well known techniques. Supporting circuitry, such as address decoders and/or controllers also may be included in a peripheral region of the ROM.
As ROM devices become more highly integrated, the number of transistors per unit area may increase, and the linewidths may be reduced. This increase in density and/or decrease in linewidth may undesirably increase resistance and/or parasitic capacitance, and may also undesirably decrease the reliability and/or yield of the devices.
FIG. 1 is a plan view of a cell region of a conventional ROM. FIGS. 2, 3, 4 and 5 are cross-sectional views which may be obtained by cutting the cell region of FIG. 1 along lines of Ixe2x80x94I, IIxe2x80x94II, IIIxe2x80x94III and IVxe2x80x94IV, respectively.
Referring to FIGS. 1-5, the entire cell region is an active region. That is, no isolation layer is formed in the cell region. High concentration N-type doping layers 20 buried in a substrate are formed as parallel lines. The surface of the substrate is covered with an insulating layer. The insulating layer includes a gate insulation layer and/or a thick insulation layer 60 on the buried high concentration N-type doping layer 20 that insulates a gate line 10 from the buried doping layer 20. The gate lines 10 are parallel lines which cross the buried doping layers 20. A first polysilicon layer pattern 50 is provided on the gate insulation layer and at a lattice region where each of the gate lines 10 crosses the parallel lines, each of which lies between the buried high concentration N-type doping layers 20. The first polysilicon layer pattern 50 provides a gate electrode at the lattice region, together with a second polysilicon layer of the gate line 10. At regions outside of the gate electrodes, the gate line 10 is composed of the second polysilicon layer. At some of the gate electrodes covered by the first polysilicon layer pattern 50, indicated by the reference number 40 of FIG. 1, a channel layer ion implantation is performed through a pattern mask. The ROM is programmed according to the ion implantation.
A Plasma Enhanced Chemical Vapor Deposition (PECVD) oxide layer 70 is stacked over the gate line 10, and a Boro-Phospo-Silicate-Glass (BPSG) layer 80 is stacked thereon to form a planarized interlayer insulation layer. A metal interconnection 30 is formed on the planarized interlayer insulation layer. In FIGS. 1-5, the metal interconnection 30 is formed once per two line patterns in parallel with the line patterns of the buried high-concentration N-type doping layer 20 and over the line patterns. A protective layer 90 is formed over the metal interconnection 30. The metal interconnection 30 provides a main bit line and is connected with the buried high concentration N-type doping layer 20, which is a sub-bit line below the metal interconnection 30, at a periphery of a selected cell transistor.
In order to select a certain memory cell, non-zero voltages may be applied on the gate line 10 passing the selected cell transistor, and on the main bit line connected with the buried high concentration N-type doping layer 20 comprising a drain region of the selected cell transistor. As a result, the voltage of the buried high concentration N-type doping layer 20 composing a source region becomes 0 V. If a threshold voltage applied on a channel region of a gate electrode bottom of the selected cell transistor is programmed to be higher than a voltage applied on the gate line 10, the cell transistor enters an xe2x80x9coffxe2x80x9d state and the bit line is not discharged, so that the cell transistor is read as xe2x80x9coffxe2x80x9d. Conversely, if the threshold voltage applied on the channel region of the selected cell transistor is programmed to be lower than the voltage applied on the gate line 10, the cell transistor enters an xe2x80x9conxe2x80x9d state and the bit line is discharged, so that the cell transistor is read as xe2x80x9conxe2x80x9d. The design, fabrication and operation of conventional ROM devices are well known to those having skill in the art and need not be described further herein.
FIGS. 6-9 are cross-sectional views of a first polysilicon layer along the gate line in a conventional ROM device, during intermediate fabrication steps.
Referring to FIG. 6, a gate insulation layer 110 of about 100 xc3x85 in thickness is formed on an integrated circuit substrate, such as a silicon semiconductor substrate 100. A first polysilicon layer 120 is stacked in a thickness of about 200 xc3x85 to about 1000 xc3x85. A capping layer 130 is formed of a silicon nitride layer, and an antireflection layer 140 is formed of a silicon oxynitride layer thereon. The resultant structure is patterned to form a line pattern composed of the antireflection layer 140, the capping layer 130, and the first polysilicon layer 120. During patterning, a partial thickness of the gate insulation layer 110 outside the line pattern is removed by over-etching.
Referring to FIG. 7, a silicon nitride layer is conformally stacked over the line pattern in a thickness of about 100 xc3x85 to about 500 xc3x85 and removed by anisotropic etching to form a sidewall spacer 160 at the sidewall of the line pattern composed of the first polysilicon layer 120 and the capping layer 130. As a partial thickness of the spacer 160 is removed by over-etching, the gate insulation layer covering the antireflection layer and the substrate also is removed. N-type ions are implanted into the substrate in a dose amount of about 1015 ions/cm2. Low ion implantation energy below 30 KeV is applied at the substrate surface to form a high concentration N-type doping layer 150 between the patterns including the first polysilicon layer 120.
Referring to FIG. 8, the substrate is thermally oxidized to form a thermal oxide layer 170 on the substrate 100, except the pattern covered with the capping layer 130. The surface of the substrate 100 is rapidly oxidized in thermal oxidation due to the earlier ion implantation, thereby volumetrically expanding. Thus, the thermal oxide layer 170 is thicker than the gate insulation layer 111 under the first polysilicon layer 120 of the pattern. The ion-implanted dopants are moved downward by the thermal oxide layer 170, to form a buried high concentration N-type doping layer 151. The first polysilicon layer 120 is covered with the capping layer 130 and the spacer 160, thereby not being oxidized.
Referring to FIG. 9, the spacer 160 and the capping layer 130 covering the first polysilicon layer 120 are removed by wet etching, and a second polysilicon layer 180 is stacked. The first polysilicon layer 120 and the second polysilicon layer 180 are patterned to form a gate line including a gate electrode. Subsequent processes are performed similar to a conventional CMOS process, and are well known to those skilled in the art. Accordingly, additional fabrication details need not be described further herein.
According to a conventional method of fabricating a ROM, the reliability of the gate insulation layer may be degraded. In particular, the gate insulation layer exists at a region V of FIG. 9, where the spacer was between the thermal oxide layers 170 covering the buried doping layer 151 and the gate insulation layer under the first polysilicon layer 120. The gate insulation layer under the first polysilicion layer 120 may be preserved during the entire process. But, in the region V, the oxide layer of the spacer bottom may become thin by partial etching during the step of forming the line pattern (FIG. 6), may become thick by the thermal oxidation step of forming the buried doping layer (FIG. 8), and again may become thin by etching at the step of removing the spacer (FIG. 9). For example, when a spacer nitride layer is removed, an oxide layer below the nitride layer may be removed in a thickness of 40 xc3x85 to 80 xc3x85. Consequently, the reliability of the gate insulation layer in the region V may be degraded and induce an operational failure and/or an insulation breakdown between the buried doping layer 151 and the second polysilicon layer 180.
Also, according to the conventional method, the antireflection layer is formed of silicon oxynitride, which may be a source of particles. Additionally, if the antireflection layer reacts with a capping layer thereunder, a portion may remain after removing the capping layer. In this case, the remaining portion may function as a blocking layer with respect to the first polysilicon layer, thereby inducing an electrical short between the gate lines.
According to some embodiments of the invention, a ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern. According to these embodiments, the thermal oxide layer that is formed on the sidewall can reduce or prevent a thinning of the insulating layer and the consequent degradation in reliability, operation and/or yield.
According to other embodiments of the invention, a sidewall spacer is not formed on the sidewall of the first conductive layer pattern between the forming of a first conductive layer and the thermally oxidizing layer. According to still other embodiments of the invention, at least a portion of the integrated circuit substrate and at least a portion of the sidewall are thermally oxidized without thermally oxidizing the top and bottom of the first conductive layer pattern.
In still other embodiments of the present invention, the first conductive layer pattern comprises a first conductive layer on the insulating layer and a capping layer on the first conductive layer. In these embodiments, the capping layer is removed after the thermal oxidizing and prior to forming the second conductive layer pattern. In other embodiments, a photoresist pattern also is formed on the capping layer, and the capping layer and the first conductive layer are etched using the photoresist pattern as an etch mask. The photoresist then may be removed.
In yet other embodiments, an antireflection layer is formed on the capping layer, and a photoresist pattern is formed on the antireflection layer. After etching, the photoresist pattern and the antireflection layer are removed. In other embodiments, the antireflection layer can comprise an organic antireflection layer. By using an organic antireflection layer, the antireflection layer may be removed completely, to thereby reduce or prevent shorting.
Integrated circuit ROM devices according to some embodiments of the invention include an integrated circuit substrate, an insulating layer on the integrated circuit substrate, and a first conductive layer pattern including a sidewall on the insulating layer opposite the integrated circuit substrate. A thermal oxide layer is on the integrated circuit substrate and directly on the sidewall of the first conductive layer pattern. A buried doping layer is in the integrated circuit substrate beneath the thermal oxide layer. A second conductive layer pattern is on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.
In still other embodiments of ROM devices, the second conductive layer line pattern is directly on the first conductive layer line pattern opposite the insulating layer. In yet other embodiments, both the first and second conductive layer patterns comprise polysilicon.